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integrated circuit systems, inc. ICS97ULP844A 1110a?05/16/05 block diagram 1.8v low-power wide-range frequency clock driver pin configuration recommended application: ddr2 memory modules / zero delay board fan out provides complete ddr dimm logic solution with icssstu32864/sstuf32864/sstuf32866 product description/features: low skew, low jitter pll clock driver 1 to 4 differential clock distribution (sstl_18) feedback pins for input to output synchronization spread spectrum tolerant inputs auto pd when input signal is at a certain logic state switching characteristics: period jitter: 40ps half-period jitter: 60ps cycle - cycle jitter 40ps output - output skew: 40ps 28-ball bga top view ball assignments a b 12 3 4 5 c d e f clkt0 clkc0 clkt1 clkc1 clkt2 clkc2 clkt3 clkc3 fb_outt fb_outc av dd fb_int clk_int clk_inc fb_inc pll powerdown control and test logic oe ld* or oe pll bypass ld* os gnd 10k-100 k * the logic detect (ld) powers down the device when a logic low is applied to both clk_int and clk_inc. 12345 a clkt0 clkc0 clkc1 clkt1 fb_int b ck_int v dd nb v dd fb_inc c ck_inc oe v dd os fb_outc d agnd gnd v dd gnd fb_outt e avdd gnd nb gnd gnd f clkc3 clkt3 clkc2 clkt2 gnd
2 ICS97ULP844A 1110a?05/16/05 pin descriptions l a n i m r e t e m a n n o i t p i r c s e d l a c i r t c e l e s c i t s i r e t c a r a h c d n g ad n u o r g g o l a n a d n u o r g v a d d r e w o p g o l a n a l a n i m o n v 8 . 1 t n i _ k l cr o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c t u p n i l a i t n e r e f f i d c n i _ k l c r o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c y r a t n e l p m o c t u p n i l a i t n e r e f f i d t n i _ b ft u p n i k c o l c k c a b d e e f t u p n i l a i t n e r e f f i d c n i _ b ft u p n i k c o l c k c a b d e e f y r a t n e m e l p m o c t u p n i l a i t n e r e f f i d t t u o _ b ft u p t u o k c o l c k c a b d e e f t u p t u o l a i t n e r e f f i d c t u o _ b ft u p t u o k c o l c k c a b d e e f y r a t n e m e l p m o c t u p t u o l a i t n e r e f f i d e o) s u o n o r h c n y s a ( e l b a n e t u p t u o t u p n i s o m c v l s ov r o d n g o t d e i t ( t c e l e s t u p t u o q d d )t u p n i s o m c v l d n gd n u o r g d n u o r g v q d d r e w o p t u p t u o d n a c i g o l l a n i m o n v 8 . 1 ] 3 : 0 [ t k l cs t u p t u o k c o l c s t u p t u o l a i t n e r e f f i d ] 3 : 0 [ c k l cs t u p t u o k c o l c y r a t n e m e l p m o c s t u p t u o l a i t n e r e f f i d b nl l a b o n the pll clock buffer, ICS97ULP844A , is designed for a v ddq of 1.8 v, a av dd of 1.8 v and differential data input and output levels. package options include a plastic 28-ball vfbga. ICS97ULP844A is a zero delay buffer that distributes a diff erential clock input pair (clk_int, clk_inc) to four differential pair of clock outputs (clkt[0:3], clkc[0:3]) and one differential pair feedback clock outputs (fb_outt, fboutc). the clock outputs are controlled by the input clocks (clk_int, clk_inc), the feedback clocks (fb_int, fb_inc), the lvcmos program pins (oe, os) and the analog power input (avdd). when oe is low, the outputs (except fb_outt/fb_outc) are disabled while the internal pll continues to maintain its locked-in frequency. os (output select) is a program pin that must be tied to gnd or v ddq . when os is high, oe will function as described above. when os is low, oe has no effect on clkt2/clkc2 (they are free running in addition to fb_outt/fb_outc). when av dd is grounded, the pll is turned off and bypassed for test purposes. when both clock signals (clk_int, clk_inc) are logic low, the de vice will enter a low power mode. an input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the pll are off. when the inputs transition from both being logic low to being differential signals, the pll will be turned back on, the inputs and outputs will be enabled and the pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_int, clk_inc) within the specified stabilization time t stab . the pll in ICS97ULP844A clock driver uses the input clocks (clk_int, clk_inc) and the feedback clocks (fb_int, fb_inc) to provide high-performance, low-sk ew, low-jitter output differential clocks (clkt[0:4], clkc[0:4]). ICS97ULP844A is also able to track spread spectrum clocking (ssc) for reduced emi. ICS97ULP844A is characterized for operation from 0c to 70c.
3 ICS97ULP844A 1110a?05/16/05 function table s t u p n is t u p t u o l l p d d v ae os ot n i _ k l ct n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n ghxl h l h l h f f o / d e s s a p y b d n ghxh l h l h l f f o / d e s s a p y b d n glhl h ) z ( l *) z ( l *lh f f o / d e s s a p y b d n gllh l , ) z ( l * 2 t k l c e v i t c a , ) z ( l * 2 c k l c e v i t c a h lf f o / d e s s a p y b ) m o n ( v 8 . 1lhlh ) z ( l *) z ( l *lh n o ) m o n ( v 8 . 1llhl , ) z ( l * 2 t k l c e v i t c a , ) z ( l * 2 c k l c e v i t c a hl n o ) m o n ( v 8 . 1hxlhlhlh n o ) m o n ( v 8 . 1hxhlhlhl n o ) m o n ( v 8 . 1xxll ) z ( l *) z ( l *) z ( l *) z ( l *f f o ) m o n ( v 8 . 1xxhh d e v r e s e r *l(z) means the outputs are disabled to a low stated meeting the i odl limit.
4 ICS97ULP844A 1110a?05/16/05 absolute maximum ratings supply voltage (vddq & avdd) . . . . . . . . . -0.5v to 2.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v ddq + 0.5v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters ta = 0 - 70c; supply voltage avddq, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units input hi g h current ( clk_int , clk_inc ) i ih v i = v ddq or gnd 250 a input low current (oe, os , fb _ int , fb _ inc ) i il v i = v ddq or gnd 10 a output disabled low current i odl oe = l, v odl = 100mv 100 a i dd1.8 c l = 0pf @ 270mhz tbd ma i ddld c l = 0pf 500 a input clamp voltage v ik v ddq = 1.7v iin = -18ma -1.2 v i oh = -100 a v ddq - 0.2 v i oh = -9 ma 1.1 1.45 v i ol =100 a 0.25 0.10 v i ol =9 ma 0.6 v in p ut ca p acitance 1 c in v i = gnd or v ddq 23pf out p ut ca p acitance 1 c out v out = gnd or v ddq 23pf 1 guaranteed b y desi g n , not 100% tested in p roduction. operating supply current high-level output voltage v oh low-level output voltage v ol
5 ICS97ULP844A 1110a?05/16/05 notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signal must be crossing. recommended operating condition ( see note1 ) t a = 0 - 70c; supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vdd 1.7 1.8 1.9 v clk_int, clk_inc, fb_inc, fb_int 0.35 x v ddq v oe, os 0.35 x v ddq v clk_int, clk_inc, fb_inc, fb_int 0.65 x v ddq v oe, os 0.65 x v ddq v dc input signal voltage (note 2) v in -0.3 v ddq + 0.3 v dc - clk_int, clk_inc, fb_inc, fb_int 0.3 v ddq + 0.4 v ac - clk_int, clk_inc, fb_inc, fb_int 0.6 v ddq + 0.4 v output differential cross- voltage (note 4) v ox v ddq /2 - 0.10 v ddq /2 + 0.10 v input differential cross- voltage (note 4) v ix v ddq /2 - 0.15 v dd /2 v ddq 2 + 0.15 v high level output current i oh -9 ma low level output current i ol 9ma operating free-air temperature t a 070c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih
6 ICS97ULP844A 1110a?05/16/05 notes: 1. switching characteristics guaranteed for application frequency range. 2. static phase offset shifted by design. timing requirements t a = 0 - 70c supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max max clock frequency freq op 1.8v+ 0.1v @ 25c 95 370 application frequency range freq app 1.8v+ 0.1v @ 25c 160 350 input clock duty cycle d tin 40 60 clk stabilization t stab 2.4 2.95 switchin g characteristics 1 t a = 0 - 70c supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol condition min typ max units output enable time t en oe to any output 4.73 8 ns output disable time t dis oe to any output 5.82 8 ns period jitter t j it (p er ) -30 30 ps half-period jitter t j it ( h p er ) -60 60 ps input clock 1 2.5 4 v/ns output enable (oe), (os) 0.5 v/ns output clock slew rate slr1 ( o ) 1.5 2.5 3 v/ns t j it ( cc+ ) 040ps t j it ( cc- ) 0 -40 ps dynamic phase offset t ( ) d y n -20 20 ps static phase offset t spo 2 -50 0 50 ps output to output skew t skew 40 ps ssc modulation frequency 30.00 33 khz ssc clock input frequency deviation 0.00 -0.50 % pll loop bandwidth (-3 db from unity gain) 2.0 mhz cycle-to-cycle period jitter input slew rate slr1(i)
7 ICS97ULP844A 1110a?05/16/05 gnd ics97ulp844 v dd v (clkc) v (clkc) scope c=10pf -vdd/2 gnd - gnd vdd/2 z=6 z = 2.97" z = 120 ? z = 2.97" 0 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? v (tt) v (tt) c = 10 pf note: v tt = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fb_outc x y , fb_outt x paramete r measuremen t informatio n ICS97ULP844A figure 3. cycle-to-cycle jitter r = 1m ? c = 1 pf r = 1m ? c = 1 pf
8 ICS97ULP844A 1110a?05/16/05 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (skew) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) t c(n) c(n) 1 f o figure 6. period jitter
9 ICS97ULP844A 1110a?05/16/05 clock inputs and outputs 80% 20% 80% 20% t slr t slf v id ,v od figure 8. input and output slew rates parameter measurement information t jit(hper_n) t jit(hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t jit(hper) t jit(hper_n) 1 2xf o =-
10 ICS97ULP844A 1110a?05/16/05 figure 9 . dynamic phase offset figure 10. time delay between oe and clock output (y, y) t ( ) t ( ) fbin fbi n ck ck t ( )dyn t ( )dyn t ( )dyn t ( )dyn ssc of f ssc on ssc on ssc off 5 0 % vddq t en t dis oe oe y/ y y 50 % vddq y y y 5 0 % vddq 50 % vd dq
11 ICS97ULP844A 1110a?05/16/05 figure 11. av dd filtering - place the 2200pf capacitor close to the pll. - use a wide trace for the pll analog power & ground. connect pll & caps to agnd trace & connect trace to one gnd via (farthest from pll). - recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.8 ohm dc max, 600 ohms @ 100 mhz).
12 ICS97ULP844A 1110a?05/16/05 ordering information ICS97ULP844A y h(lf)-t example: designation for tape and reel packaging annealed lead free (optional) package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y h (lf)- t min nom max min nom max a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0.165 0.20 0.235 0.006 0.008 0.009 a2 0.16 0.20 0.24 0.006 0.008 0.009 a3 0.475 0.50 0.525 0.019 0.020 0.021 b 0.35 0.40 0.45 0.014 0.016 0.018 d 3.90 4.00 4.10 0.154 0.157 0.161 d1 e 4.40 4.50 4.60 0.173 0.177 0.181 e1 e symbol 3.25 bsc 0.65 bsc 0.128 bsc 0.026 bsc millimeter inch 0.102 bsc 2.60 bsc

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